Design of High-Performance CMOS Voltage-Controlled Oscillators (The Springer International Series in Engineering and Computer Science)
| Author | : | |
| Rating | : | 4.29 (563 Votes) |
| Asin | : | 1402072384 |
| Format Type | : | paperback |
| Number of Pages | : | 158 Pages |
| Publish Date | : | 2016-12-21 |
| Language | : | English |
DESCRIPTION:
"great book" according to Bortecene Terlemez. One of the best books I read lately Finished it in one night couldn't drop it off my hands. Step on the author's feet, and take a walk through their experiences Theory design sim measurement and their interaction I've got a PhD on PLLs, I still had to say "wow" when I was reading this very well written book. Highly recommend it ;o)
Our phase noise analysis is validated via simulation and measurement results.The digital switching noise coupled through the power supply and substrate is usually the dominant source of clock jitter. It indicates that fast rail-to-rail switching has to be achieved to minimize phase noise. We define the effective Q factor (Qeff) for ring oscillators and predict its increase for CMOS processes with smaller feature sizes. Improving the supply and substrate noise immunity of a PLL is a challenging job in hostile environments such as a microprocessor chip where millions of digital gates are present.. The analysis considers both linear and nonlinear operation. Design of High-Performance CMOS Voltage-Controlled Oscillators presents a phase noise modeling framework for CMOS ring oscillators. Additionally, in conventional design the flicker noise in the bias circuit can potentially dominate the phas